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1 ? fn6353.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. isl97645a boost + v on slice + v com + reset the isl97645a represents an integrated dc/dc regulator for monitor and notebook applications with screen sizes up to 20?. the device integrat es a boost converter for generating a vdd , a v on slice circuit, and a high performance v com amplifier. the boost converter features a 2.6a fet and has user programmable soft-start and compensation. with efficiencies up to 92%, the a vdd is user selectable from 7v to 20v. the v on slice circuit can control gate voltages up to 30v. high and low levels are programmable, as well as discharge rate and timing. the supply monitor can be used to monitor the input voltage to prevent low voltage operation. the integrated v com features high speed and drive capability. with 30mhz bandwidth and 50v/s slew rate, the v com amplifier is capable of driving 400ma peaks, and 100ma continuous output current. features ? 2.7v to 5.5v input ? 2.6a integrated boost for up to 20v a vdd ? integrated v on slice ? reset signal generated by supply monitor ? 600khz/1.2mhz f s ?v com amplifier -30mhz bw -50v/s sr - 400ma peak output current ? uv and ot protection ? 24 ld 4x4 qfn ? pb-free (rohs compliant) applications ? lcd monitors (15?+) ? notebook display (up to 16?) pinout isl97645a (24 ld 4x4 qfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl97645airz 976 45airz -40 to +85 24 ld 4x4 qfn l24.4x4d notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97645a . for more information on msl please see techbrief tb363 . vgh re ce pgnd fb enable out neg pos agnd cd2 vdiv gnd vgh_m vflk vdpm vdd1 vdd2 lx vin2 freq2 comp ss reset 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 data sheet october 21, 2010
2 fn6353.1 october 21, 2010 pin descriptions pin number name description 1 gnd signal ground 2 vgh_m gate pulse modulator output 3 vflk gate pulse modulator control input 4 vdpm gate pulse modulator enable. connect a capacitor fr om vdpm to gnd to set the delay time before gpm is enabled. a 20 a current source charges cdpm. power on delay time = 60.75k*cdpm. 5 vdd1 gate pulse modulator low voltage input 6 vdd2 vcom amplifier supply 7 out vcom amplifier output 8 neg vcom amplifier inverting input 9 pos vcom amplifier non-inverting input 10 agnd vcom amplifier ground 11 cd2 voltage detector rising edge delay. connect a capacito r between this pin and gnd to set the rising edge delay. 12 vdiv voltage detector threshold. connect to t he center of a resistive divider between v in and gnd. 13 reset voltage detector reset output. 14 ss boost converter soft-start. connect a capacitor between this pin and gnd to set the soft-start time. 15 comp boost converter compensation pin. connect a seri es resistor and capacitor between this pin and gnd to optimize transient response. 16 freq boost converter frequency select 17 vin2 boost converter power supply 18 lx boost converter switching node 19 enable chip enable pin. connect to vin1 for normal operation, gnd for shutdown. 20 fb boost converter feedback 21 pgnd boost converter power ground 22 re gate pulse modulator slew control. connect a resist or between this pin and gnd to set the falling slew rate. 23 ce gate pulse modulator delay control. connect a capacitor between this pin and gnd to set the delay time. 24 vgh gate pulse modulator high voltage input isl97645a
3 fn6353.1 october 21, 2010 absolute maximum rati ngs thermal information lx to gnd, agnd and pgnd . . . . . . . . . . . . . . . . . . . . -0.5 to +25v vdd2, out, neg and pos to gnd, agnd and pgnd. . . . . . . . . . . . . . . . . . . . . -0.5 to +25v vdd1, vgh and vgh_m to gnd, agnd and pgnd. . . . . . . . . . . . . . . . . . . . . -0.5 to +32v differential voltage between pos and neg . . . . . . . . . . . . . . . 6v voltage between gnd, agnd and pgnd . . . . . . . . . . . . . . . 0.5v all other pins to gnd, agnd and pgnd . . . . . . . . . . -0.5 to +6.5v input, output, or i/o voltage . . . . . . . . . . . gnd -0.3v to vin + 0.3v recommended operating conditions input voltage range, vs . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v boost output voltage range, av dd . . . . . . . . . . . . . . . . . . 8v to 20v input capacitance, c in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22f boost inductor, l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3h to 10h output capacitance, c out . . . . . . . . . . . . . . . . . . . . . . . .2f x 22f operating ambient temperature range . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . .-40c to +125c thermal resistance ja (c/w) jc (c/w) 4x4 qfn package (notes 4, 5) . . . . . . 39 2.5 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum continuous junction temperature . . . . . . . . . . . +125c power dissipation t a +25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44w t a = +70c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34w t a = +85c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98w t a = +100c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61w pb-free reflow profile see link below http://www.inters il.com/pbfree/pb -freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v in = enable = 5v, v dd1 =v dd2 = 14v, v gh = 25v, av dd = 10v, t a = -40c to +85c unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test condition min (note 6) typ max (note 6) unit general v s v in input voltage range 2.7 3.3 5.5 v i s_dis v in supply currents when disabled enable = 0v 1 3.5 a i s v in supply currents enable = 5v, lx not switching 1 ma uvlo under voltage lockout threshold v in2 rising 2.3 2.45 2.6 v v in2 falling 2.2 2.35 2.5 v ot r thermal shutdown temperature temperature rising 140 c ot f temperature falling 100 c logic input characteristics - enable, vflk, freq, vdpm v il low voltage threshold 0.8 v v ih high voltage threshold 2.2 v r il pull-down resistor enabled, input at v in 150 250 400 k step-up switching regulator a vdd output voltage range v in *1.25 20 v vboost/ iout load regulation 50ma < i load < 250ma 0.2 % vboost/ vin line regulation i load = 150ma, 3.0 < v in < 5.5v 0.15 0.25 % acc avdd overall accuracy (line, load, temperature) 10ma < i load < 300ma, 3.0 < v in < 5.5v, 0c < t a < +85c -3 3 % v fb feedback voltage (v fb )i load = 100ma, t a = +25c 1.20 1.21 1.22 v i load = 100ma, t a = -40c to +85c 1.19 1.21 1.23 v isl97645a
4 fn6353.1 october 21, 2010 i fb fb input bias current 250 500 na r ds(on) switch on-resistance 150 300 m eff peak efficiency 92 % i lim switch current limit 2.9 a d max max duty cycle 85 90 % f osc oscillator frequency freq = 0v 550 650 800 khz freq = v in2 1.0 1.2 1.4 mhz i ss soft-start slew current ss < 1v, t a = +25c 2.75 a v com amplifier r load =10k, c load = 10pf, unless otherwise stated v samp supply voltage 4.5 20 v i samp supply current 3ma v os offset voltage 3 20 mv i b noninverting input bias current 0 100 na cmir common mode input voltage range 0 vdd2 v cmrr common-mode rejection ratio 50 70 db psrr power supply rejection ratio 70 85 db v oh output voltage swing high i out (source) = 5ma vdd2 - 50 mv v oh output voltage swing high i out (source) = 50ma vdd2 - 450 mv v ol output voltage swing low i out (sink) = 5ma 50 mv v ol output voltage swing low i out (sink) = 50ma 450 mv i sc output short circuit current 250 400 ma sr slew rate 50 v/s bw gain bandwidth -3db gain point 30 mhz gate pulse modulator v gh vgh voltage 730 v v ih_vdpm v dpm enable threshold 1.18 1.215 1.25 v i vgh vgh input current vflk = 0 260 a re = 33k , vflk = vdd1 40 a v dd1 vdd1 voltage 3vgh - 2 v i vdd1 vdd1 input current -2 0.1 2 a r onvgh vgh to vgh_m on resistance 70 i dis_vgh vgh_m discharge current re = 33k 8ma idpm vdpm charge current 20 a t del delay time ce = 470pf, re = 33k 1.9 s electrical specifications v in = enable = 5v, v dd1 =v dd2 = 14v, v gh = 25v, av dd = 10v, t a = -40c to +85c unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test condition min (note 6) typ max (note 6) unit isl97645a
5 fn6353.1 october 21, 2010 i supply monitor v ih_vdiv vdiv high threshold vdiv rising 1.18 v v il_vdiv vdiv low threshold vdiv falling 1.05 v i cd2 cd2 charge current 10 a r il_reset reset pull-down resistance 750 t delay_reset reset delay on the rising edge 121.5k*cd s note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications v in = enable = 5v, v dd1 =v dd2 = 14v, v gh = 25v, av dd = 10v, t a = -40c to +85c unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test condition min (note 6) typ max (note 6) unit typical performance curves figure 1. a vdd efficiency vs ia vdd figure 2. a vdd load regulation vs ia vdd figure 3. line regulation a vdd vs v in figure 4. boost conver ter transient response 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 ia vdd (ma) efficiency (%) f osc = 1.2mhz f osc = 650khz -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 200 400 600 800 1000 1200 ia vdd (ma) load regulation (%) f osc = 1.2mhz f osc = 650khz 10.15 10.2 10.25 10.3 10.35 10.4 10.45 10.5 3 3.5 4.0 4.5 5.0 5.5 6.0 v in (v) a vdd (v) a vdd 500ma a vdd 150ma ia vdd a vdd (ac coupled) l = 10h, c out = 40f, c comp = 2.2nf, r comp = 10k isl97645a
6 fn6353.1 october 21, 2010 figure 5. gpm circuit waveform figure 6. gpm circuit waveform figure 7. gpm circuit waveform figure 8. gpm circuit waveform figure 9. v ghm follows v gh when the system powers off figure 10. v com rising slew rate typical performance curves (continued) vgh_m vflk ce = 1pf, re = 100k vgh_m vflk ce = 1000pf, re = 100k vgh_m vflk ce = 10pf, re = 100k vgh_m vflk ce = 10pf, re = 150k input signal output signal isl97645a
7 fn6353.1 october 21, 2010 figure 11. v com bandwidth measurement typical performance curves (continued) input output signal signal (-3db attentuation from input signal) isl97645a
8 fn6353.1 october 21, 2010 block diagram figure 12. isl97645a block diagram + - vflk vgh ce re vgh_m lx pgnd enable fb comp freq oscillation slope compensation generator reference generator summing amplifier start-up and fault control + - pwm logic ss 2.5a reset vin vdpm out vdd2 pos neg gnd vdd1 + - gpm circuit 20a 10a + - cd2 v ref + - vdiv v ref 750 isl97645a
9 fn6353.1 october 21, 2010 functional block diagram applications information the isl97645a provides a complete power solution for tft lcd applications. the system consists of one boost converter to generate a vdd voltage for column drivers, one integrated v com buffer which can provide up to 400ma peak current, and one supply monitor to generate the reset signal when the input voltage is low. th is part also integrates gate pulse modulator circuit that can help to optimize the picture quality. enable control when enable pin is pulling down, the isl97645a is shut down reducing the supply current to <10a. when the voltage at enable pin reaches 2.2v, the isl97645a is on. boost converter frequency selection the isl97645a switching frequency can be user selected to operate at either constant 650khz or 1.2mhz. lower switching frequency can save power dissipation, while higher switching frequency can allow smaller external components like inductor and output capacitors, etc. connecting the freq pin to gnd sets the pwm switching frequency to 650khz, or connecting freq pin to v in for 1.2mhz. soft-start the soft-start is provided by an internal 2.5a current source to charge the external soft-start capacitor. the isl97645a ramps up current limit from 0a up to full value, as the voltage at ss pin ramps from 0 to 1.2v. hence the soft-start time is 4.8ms when the soft-start capacitor is 10nf, 22.6ms for 47nf and 48ms for 100nf. figure 13. functional block diagram boost gpm circuit v on a vdd vshdn vgh vdd1 vgh_m lx fb vflk comp ss pos cd2 vdiv reset gnd vdpm freq- ce re pgnd vdd2 agnd vin neg- v gate ref out vin v in vin isl97645a
10 fn6353.1 october 21, 2010 operation the boost converter is a current mode pwm converter operating at either a 650khz or 1.2mhz. it can operate in both discontinuous conduction mode (dcm) at light load and continuous mode (ccm). in continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady st ate operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. figure 12 shows the block diagram of the boost regulator. it uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comparator looks at the peak inductor current cycle by cycle and term inates the pw m cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k is recommended. the boost converter output voltage is determined by equation 2: the current through the mosfet is limited to 2.6a peak . this restricts the maximum ou tput current (average) based on equation 3: where i l is peak to peak inductor ripple current, and is set by equation 4: where f s is the switching frequency (650khz or 1.2mhz). table 2 gives typical values (m argins are considered 10%, 3%, 20%, 10% and 15% on v in , v o , l, f s and i omax ). capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converte r. the ceramic capacitor with capacitance larger than 10f is recommended. the voltage rating of input capacitor shoul d be larger than the maximum input voltage. some capacitors are recommended in table 1 for input capacitor. v boost v in ------------------ - 1 1d ? ------------- = (eq. 1) v boost r 1 r 2 + r 2 -------------------- - v fb = (eq. 2) table 1. boost converter input capacitor recommendation capacitor size mfg part number 10f/16v 1206 tdk c3216x7r1c106m 10f/10v 0805 murata grm21br61a106k 22f/10v 1210 murata grb32er61a226k i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- = (eq. 3) i l v in l --------- d f s ---- = (eq. 4) table 2. maximum output current calculation v in (v) v o (v) l (h) f s (mhz) i omax (ma) 3 9 10 0.65 636 3 12 10 0.65 419 3 15 10 0.65 289 5 9 10 0.65 1060 5 12 10 0.65 699 5 15 10 0.65 482 5 18 10 0.65 338 3 9 10 1.2 742 3 12 10 1.2 525 3 15 10 1.2 395 5 9 10 1.2 1236 5 12 10 1.2 875 5 15 10 1.2 658 5 18 10 1.2 514 isl97645a
11 fn6353.1 october 21, 2010 inductor the boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. values of 3.3h to 10h are used to match the internal slope compensation. the indu ctor must be able to handle the following average and peak current are in equation 5: some inductors are recommended in table 3. rectifier diode a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output voltage. the re ctifier diode must meet the output current and peak inductor current requirements. the following table is some recommendations for boost converter diode. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: 1. the voltage drop due to the inductor ripple current flowing through the esr of output capacitor. 2. charging and discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. c out in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer?s stated value, measured at 0v. table 5 shows some selections of output capacitors. compensation the boost converter of isl97645a can be compensated by a rc network connected from cm1 pin to ground. 4.7nf and 10k rc network is used in the demo board. the larger value resistor and lower value capacitor can lower the transient overshoot, however, at the expense of stability of the loop. cascaded mosfet application an 20v n-channel mosfet is integrated in the boost regulator. for the applications where the output voltage is greater than 20v, an external cascaded mosfet is needed as shown in figure 14. the voltage rating of the external mosfet should be greater than a vdd . table 3. boost inductor recommendation inductor dimensions (mm) mfg part number 6.8h/3a peak 7.3x6.8x3.2 tdk rlf7030t-6r8n3r0 10h/4a peak 8.3x8.3x4.5 sumida cdr8d43-100nc 5.2h/4.55a peak 10x10.1x3.8 cooper bussmann cd1-5r2 table 4. boost converter rectifier diode recommendation diode v r /i avg rating package mfg ss23 30v/2a smb fairchild semiconductor mbrs340 40v/3a smc international rectifier sl23 30v/2a smb vishay semiconductor i lavg i o 1d ? ------------- = i lpk i lavg i l 2 -------- + = (eq. 5) v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s --- - + = (eq. 6) table 5. boost output capacitor recommendation capacitor size mfg part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k figure 14. cascaded mosfet topology for high output voltage applications intersil isl97645a lx fb a vdd v in isl97645a
12 fn6353.1 october 21, 2010 supply monitor circuit the supply monitor circuit monitors the voltage on vdiv, and sets open-drain output reset low when vdiv is below 1.15v (rising) or 1.1v (falling). there is a delay on the rising edge, controlled by a capacitor on cd2. when vdiv exceeds 1.15v (rising), cd2 is charged up from 0v to 1.215v by a 10a current source. once cd2 exceeds 1.215v, reset will go tri-state. when vdiv falls below 1.1v, reset will become low with a 750 pull-down resistance. the delay time is controlled by equation 7: for example, the delay time is 12.15ms if the cd2 = 100nf. figure 15 is the supply monitor circuit timing diagram. gate pulse modulator circuit the gate pulse modulator circuit functions as a three way multiplexer, switching vghm between ground, vdd1 and vgh. voltage selection is provided by digital inputs vdpm (enable) and vflk (control). high to low delay and slew control is provided by external components on pins ce and re, respectively. a block diagram of the gate pulse modulator circuit is shown in figure 16. when vdpm is low, the block is disabled and vghm is grounded. when the input voltage exceeds uvlo threshold, vdpm starts to drive an external capacitor with 20 a. once vdpm exceeds 1.215v, the gpm circuit is enabled, and the output vgh_m is determined by vflk, reset signal and vgh voltage. if reset signal is high, and when vflk goes high, vghm is pulled to vgh by a 70 switch. when vflk goes low, there is a delay controlled by capacitor ce, following which vghm is driven to vdd1, with a slew rate controlled by resistor re. note that vdd1 is used only as a reference voltage for an amplifier, thus does not have to source or sink a significant dc current. low to high transition is determined primarily by the switch resistance and the external capacitive load. high to low transition is more co mplex. take the case where the block is already enabled (vdpm is h). when vflk is h, pin ce is grounded. on the falling edge of vflk, a current is passed into pin ce, to charge an external capacitor to 1.2v. this creates a delay, equal to ce*4200. at this point, the output begins to pull down from vgh to vdd1. the slew current is equal to 300/(re + 5000), and the dv/dt slew rate is isl/c load . where c load is the load capacitance applied to vghm. when reset signal changes to low, and vgh voltage is above 2.5v, the vgh_m will be tied to vgh voltage until the vgh voltage falls down to 2.5v. if the vgh voltage is lower than 2.5v, gpm block will not work properly, and there is no active control for vgh_m output. the following table shows the vgh_m status based on v in , vgh and reset: t delay 121.5k cd2 = (eq. 7) figure 15. supply monitor circuit timing diagram vdiv reset 1.15v 1.1v 1.215v cd2 reset delay time is controlled by cd2 capacitor isl97645a
13 fn6353.1 october 21, 2010 . figure 16. gate pulse modulator circuit block diagram vgh_m vgh vgh_m vdd1 re ce vflk engpm1 vref control timing and x240 200a vin 0 uvlo threshold vdpm 1.215v vflk vgh_m vgh vgl vgh_m is forced to vgh when reset goes to low and vgh>2.5v delay tim e is controlled by ce power on delay time is controlled by c dpm slope is controlled by re vgh reset figure 17. gate pulse modulator timing diagram isl97645a
14 fn6353.1 october 21, 2010 start-up sequence when v in exceeds vlor and enable reaches the vih threshold value, boost conver ter starts up, and gate pulse modulator circuit output hold s until vdpm is charged to 1.215v. note that there is a dc path in the boost converter from the input to the output through the inductor and diode, hence the input voltage will be seen at output with a forward voltage drop of diode before the part is enabled. if this voltage is not desired, the following circuit can be inserted between input and inductor to disconnect the dc path when the part is disabled. . v com amplifier the v com amplifier is designed to control the voltage on the back plate of an lcd display. this plate is capacitively coupled to the pixel drive vo ltage which alternately cycles positive and negative at the line rate for the display. thus the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few 100ma for typical applications). the isl97645a v com amplifier's output cu rrent is limited to 400ma. this limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. it does not necessarily prevent a large temperature rise if the current is maintained. (in this case the whole chip may be shut down by the thermal trip to protect functionality.) if the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. this will happen on the s time scale in practical systems and for pulses 2 or 3 times the current limit, the v com voltage will have settled again before the next line is processed. fault protection isl97645a provides the overall fault protections including over current protection and over-temperature protection. an internal temperature sens or continuously monitors the die temperature. in the event that die temperature exceeds the thermal trip point, the device will shut down and disable itself. the upper and lower trip points are typically set to +140c and +100c respectively. table 6. vgh_m status table v in vdpm reset vgh vgh_m comment x x x <2.5v ground will be grounded if vin is above a logic threshold. could occur at power-up or power-down >vlor <1.215v x >2.5v ground start-up only condition: if either v in > vlor or reset is h, but vdpm < 1.215v, gnd vghm x <1.215v high >2.5v ground >vlor >1.215v high >2.5v switching controlled by vflk x x low >2.5v vgh power-down state. could occur at power-up if part starts with vgh > 2.5v figure 18. circuit to disconnect the dc path of boost converter input enable to inductor isl97645a
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6353.1 october 21, 2010 layout recommendation the device?s performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. there are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v in and vdd bypass capacitors close to the pins. 3. reduce the loop area with large ac amplitudes and fast slew rate. 4. the feedback network should sense the output voltage directly from the point of load, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at only one point. 6. the exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. a signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for control circuit. 9. minimize feedback input track lengths to avoid switching noise pick-up. a demo board is available to illustrate the proper layout implementation. isl97645a
16 fn6353.1 october 21, 2010 isl97645a package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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